Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL1. ECE Department, Hindusthan College of Engineering & Technology, Coimbatore 6. India. 2Department of Electrical Sciences, Adithya Institute of Technology, Coimbatore 6. India. 3Maharaja Institute of Technology, Coimbatore 6. India. 4ECE Department, Coimbatore Institute of Technology, Coimbatore 6. India. Copyright . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 1. MHz to 3. 00 MHz. Servicing All Suburbs & Perth Hills. Bobcat Perth is a privately owned earthmoving business proudly serving all suburbs in Perth, and Perth Hills. Clients can be assured that we are committed to providing quality workmanship. 5 5 Write Matlab Program for Dynamic range compression &Bit plane slicing 6 Write Matlab Program for Histogram Processing 7 Write Matlab Program for Image smoothing. 8 Write Matlab Program for Image sharpening. Introduction. Over the past few decades, low power design solution has steadily geared up the list of researcher’s design concerns for low power and low noise digital circuits to introduce new methods to the design of low power VLSI circuits. Moore’s law describes the requirement of the transistors for VLSI design which gives the experimental observation of component density and performance of integrated circuits, which doubles every two years. Transistor count is a primary concern which largely affects the design complexity of many function units such as multiplier and arithmetic logic unit (ALU). The significance of the digital computing lies in the multiplier design. The multipliers play a significant role in arithmetic operations in DSP applications. Recent developments in processor designs also focus on low power multiplier architecture usage in their circuits. Two significant yet often conflicting design criteria are power consumption and speed. Taking into consideration these constraints, the design of low power multiplier is of great interest. For instance, 2. N2. N2. P, PFAL, pass transistor adiabatic logic, clocked adiabatic l. Logic, improved pass- gate adiabatic logic, and adiabatic differential switch Logic were designed and achieved considerable energy savings, compared with conventional CMOS design . Many research methods in the adiabatic logic have been attempted to reduce the power dissipation of VLSI circuits, reported in . Many research efforts in the multiplier design have been introduced to obtain energy efficiency in VLSI circuits. By the scaling rules set by Dennard, smart optimization can be achieved by means of timely introduction of new processing techniques in device structures and materials .
III BTECH ECE 1 GVPCOE AUTONOMOUS FOR 2009 ADMITTED BATCH MATHEMATICS – III Course Code: ABM1104 L T P C 4 1 0 4 Aim: To acquire basic knowledge in the theory of functions. In this paper, design of low power multiplier with energy efficient full adder using double pass transistor asynchronous adiabatic logic (DPTAAL) is proposed and discussed in further sections. Adiabatic Logic Design “Adiabatic” is a term of Greek origin which spent most of its history related to classical thermodynamics. It refers to a system in which a transition occurs without energy (usually in the form of heat) being either lost to or gained from the system. In the context of use of electronic systems, electronic charge is preserved rather than heat. Adiabatic logic is viewed on issues related to the thermodynamics of computation. By considering this branch of physics that usually looks at mechanical engines and applying it to computing engines, research areas such as reversible computation as well as adiabatic logic have been developed. By moving to a computing paradigm that is reversible, energy can be reprocessed from a computing engine and reused to perform further calculations. This style of logical approach differs from CMOS circuits, which dissipate energy during switching. To reduce the dynamic power, there are some conventional approaches such as reducing supply voltage, decreasing physical capacitance, and reducing switching activity. These approaches are not conforming enough to meet today’s power requirement. On the other hand, most research has focused on building adiabatic logic, which is a hopeful design for low power applications. Adiabatic technique works with the concept of switching activities which reduces the power by giving stored energy back to the supply. Thus, the term adiabatic logic is applied in low power VLSI circuits which execute reversible logic. In the adiabatic techniques, the main design changes are focused on power clock which plays the essential role in the principle of operation. The following major design rules for the adiabatic circuit design are achieved in each phase of the power clock. Never turn on a transistor if voltage exists across it . Never turn off a transistor if current exists across it . Never pass current through a diode. In all the four phases of power clock, if these conditions are satisfied, recovery phase will restore the energy to the power clock, resulting in considerable energy saving. Even some complexities in adiabatic logic design perpetuate. Two such complexities are circuit implementation for time- varying power sources that needs to be done and computational implementation by low overhead circuit structures that needs to be followed . Asynchronous Adiabatic Logic (AAL)Asynchronous adiabatic logic is a unique design technique which combines the energy saving benefits of asynchronous logic and adiabatic logic. Like adiabatic circuits, asynchronous circuits are also a promising technology to focus on low power, highly modular digital circuits. One of the properties of asynchronous systems which make them useful in these applications is that circuits include a built- in insensitivity to variations in power supply voltage, with a lower voltage resulting in slower operation rather than the functional failures that would be seen if traditional synchronous systems were used. Another benefit is the fact that when an asynchronous system is idle, it will not utilize clock signals, whereas in synchronous systems, these clock signals are propagated throughout the entire system and convert energy to heat, often without performing any useful computations. In contrast to the synchronous circuits, asynchronous circuits perform handshaking between their components to perform all necessary synchronization, communication, and sequencing of operations. Asynchronous circuits fall into different classes, each offering different advantages. The main privilege of this circuit is its low power consumption, stemming from its elimination of clock drivers and the fact that no transistor ever transitions unless it is performing a useful computation. Proposed Design. The main objective of this paper is to design low power multiplier with energy efficient full adder cell using double pass transistor with asynchronous adiabatic logic. The logic scheme for full adder cell is illustrated in Figure 1. In this, entire system consists of two main blocks, such as logical block and control and regeneration (C& R) block. Figure 1: Logic scheme for fulladder cell. As in Figure 1, data output signal of any logical block is not only going into next logical block as data input, but at the same time, it is used to generate a control signal for the next logical block using C& R block 1 as reported in . This technique helps to save the required power clock generator with less power. Power Clock. In adiabatic circuits, the supply voltage behaves as the clock of the circuit by providing the power, to the circuit and for this reason, it is called power clock. One of the main concerns in the adiabatic logic circuits is the power clock generation. In these circuits, the supply voltage is desired to be a ramping voltage. In the conventional synchronous adiabatic circuits, rather driving each adiabatic logic unit with an externally supplied clock phase, each block is controlled and powered by control signal generated by the C& R block with the help of the logical output of the previous stage. In the design of VLSI circuits, power clock design is a major issue, because the whole transistor logic system shares the power clock. The power clock switching circuit will also dissipate the most power in the logic. Nowadays multiple phase clocks and clock pipelining are the most followed techniques to reduce power dissipation in the power clocks. The synchronous clock system utilizes the clock source globally; that is, single clock is shared and restored by the large number of logical gates in parallel. Here switching loss of the power clock generator is more as in the CMOS circuit operation. The simple construction of the pass transistor logic makes it easy to adjust the sizing of transistors to get the desired charging and discharging time; hence the slope of the output control signal minimizes the power. The clock energy in the asynchronous clock system is locally stored in the C& R block, and it has been used for later gates; the loss of energy of each operation will be taken from its clock source. The local regeneration stores the intermediate energy. This energy is provided to the required operations for the next level of logic. However, the initial requirement of power from the clock generator remains the same; after powering up the logical sequence, power taken from the power clock is reduced drastically. The proposed multiplier design scheme is illustrated in Figure 2.
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